Secured AES 256 Using Verilog

Authors

  • Ms.Rachana M.K Author

Keywords:

Advanced Encryption Standard, Low Power, Secured, Key Size, S Box.

Abstract

Although many algorithms were originally developed to encrypt and decode data, previous methods are not effective in protecting large amounts of sensitive information. As a result, AES was developed as a new standard for data encryption and decryption. AES was initially used primarily to encrypt highly sensitive data, but later became the industry standard for data protection for many Internet applications. Its main purpose is to protect sensitive data, and it is sometimes used to improve data security in backend network systems. Verilog offers much faster runtime and propagation delay for both data encoding and decoding than other HDL languages, which is the main argument for switching from standard VHDL to it. Before AES, DES was used as the encryption standard. The main drawback of DES is that the fixed key size of 56 bits. To make it more secured AES with key size 256bit size used.

 

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Published

2025-03-11

How to Cite

Secured AES 256 Using Verilog. (2025). IES International Journal of Multidisciplinary Engineering Research, 1(1), 37-44. https://iescepublication.com/index.php/iesijmer/article/view/5